1. Field of the Invention
The present invention relates to a circuit and a method for generating a synchronous signal.
2. Description of the Related Art
An image processing apparatus such as a television set, a computer, or the like comprises a synchronous signal generation circuit for generating an internal horizontal synchronous signal and an internal vertical synchronous signal.
The image processing apparatus processes an image signal with using the internal horizontal synchronous signal and the internal vertical synchronous signal generated by the synchronous signal generation circuit, and displays an image on a display unit such as a CRT (Cathode Ray Tube) or the like.
The synchronous signal generation circuit generates the internal horizontal synchronous signal and the internal vertical synchronous signal by using an external horizontal synchronous signal and an external vertical synchronous signal from the outside.
The technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H7-87461 forcibly controls an internal synchronous signal to synchronize with an external synchronous signal in each field, in a case where a difference between the phases of the external synchronous signal and internal synchronous signal exceeds a tolerable level.
In a case where external synchronous signals (an external vertical synchronous signal and an external horizontal synchronous signal) and internal synchronous signals (an internal vertical synchronous signal and an internal horizontal synchronous signal) are controlled to synchronize with each other in each field just as controlled to synchronize by the technique in the above-indicated publication, a difference between phases in each horizontal scanning period is carried over to the following horizontal scanning periods, so that differences between phases are accumulated in a period of one field, as shown in FIG. 10. Such the technique might not be able to display a high-quality image.
The content of Unexamined Japanese Patent Application KOKAI Publication No. H7-87461 is incorporated herein by reference.
Accordingly, it is an object of the present invention to provide a synchronous signal generation circuit and a synchronous signal generation method for displaying a high-quality image.
To accomplish the above object, a synchronous signal generation circuit according to a first aspect of the present invention comprises:
a first counter which counts pulses of a first clock signal in every first cycle of a supplied first horizontal synchronous signal repeatedly;
a second counter which repeatedly counts pulses of a second clock signal in every predetermined second cycle, and generates a second horizontal synchronous signal having the second cycle; and
a first controller which controls the second horizontal synchronous signal to synchronize with the first horizontal synchronous signal by controlling the second counter in accordance with a difference between a first value counted by the first counter, and a second value counted by the second counter.
According to this invention, a high-quality image can be displayed.
The first counter may generate a first pulse signal having the first cycle, as well as counting pulses of the first clock signal.
The second counter may generate a second pulse signal having the second cycle, as well as generating the second horizontal synchronous signal.
The synchronous signal generation circuit may further comprise:
a third counter which repeatedly counts pulses of the first pulse signal in every third cycle of a supplied first vertical synchronous signal;
a fourth counter which repeatedly counts pulses of the second pulse signal in every predetermined fourth cycle, and generates a second vertical synchronous signal having the fourth cycle; and
a second controller which controls the second vertical synchronous signal to synchronize with the first vertical synchronous signal by controlling the fourth counter in accordance with a difference between a third value counted by the third counter and a fourth value counted by the fourth counter.
The first controller may control a phase of the second horizontal synchronous signal to substantially be equal to a phase of the first horizontal synchronous signal by controlling the second counter so that an absolute value of the difference between the first value and the second value is equal to or smaller than a first preset value.
The first controller may stop an operation of the second counter for a predetermined period in a case where a value obtained by subtracting the first value from the second value is greater than the first preset value, and may control the operation of the second counter to jump in a case where the value obtained by subtracting the first value from the second value is smaller than a minus value of the first preset value.
The second controller may control a phase of the second vertical synchronous signal to substantially be equal to a phase of the first vertical synchronous signal by controlling the fourth counter so that an absolute value of the difference between the third value and the fourth value is equal to or smaller than a second preset value.
The second controller may stop an operation of the fourth counter for a predetermined period in a case where a value obtained by subtracting the third value from the fourth value is greater than the second preset value, and may control the operation of the fourth counter to jump in a case where the value obtained by subtracting the third value from the fourth value is smaller than a minus value of the second preset value.
The synchronous signal generation circuit may further comprise a signal supplier which supplies the second pulse signal generated by the second counter to the fourth counter.
The second controller may control the fourth counter by controlling an operation of the signal supplier.
The second controller may control the signal supplier so that an absolute value of the difference between the third value and the fourth value is equal to or smaller than a second preset value.
By controlling the signal supplier, the second controller may stop a supply of the second pulse signal for a predetermined period in a case where a value obtained by subtracting the third value from the fourth value is greater than the second preset value, and may successively supply a predetermined number of pulses of the second pulse signal to the fourth counter in a case where the value obtained by subtracting the third value from the fourth value is smaller than a minus value of the second preset value.
The synchronous signal generation circuit may further comprise a delay circuit which delays the first value counted by the first counter, and the third value counted by the third counter.
The first controller may control the second counter in accordance with a difference between the delayed first value and the second value.
The second controller may control the fourth counter in accordance with a difference between the delayed third value and the fourth value.
A synchronous signal generation circuit according to a second aspect of the present invention comprises:
a first counter which repeatedly counts pulses of a first clock signal in every first cycle of a supplied first horizontal synchronous signal, and generates a first pulse signal having the first cycle;
a second counter which repeatedly counts pulses of a second clock signal in every predetermined second cycle, generates a second horizontal synchronous signal having the second cycle, and generates a second pulse signal having the second cycle;
a third counter which repeatedly counts pulses of the first pulse signal in every third cycle of a supplied first vertical synchronous signal;
a fourth counter which repeatedly counts pulses of the second pulse signal in every predetermined fourth cycle, and generates a second vertical synchronous signal having the fourth cycle;
a control signal supplier which generates a control signal for controlling an operation of the second counter or the fourth counter in accordance with a difference between a first value counted by the first counter and a second value counted by the second counter, or in accordance with a difference between a third value counted by the third counter and a fourth value counted by the fourth counter, and supplies the control signal to the second counter or to the fourth counter;
a first selector which selects one of the first value and the third value, and one of the second value and the fourth value, and supplies the selected values to the control signal supplier; and
a second selector which selects one of the second counter and the fourth counter as a target to be supplied with the control signal,
wherein:
the second counter generates the second horizontal synchronous signal synchronizing with the first horizontal synchronous signal in accordance with the control signal; and
the fourth counter generates the second vertical synchronous signal synchronizing with the first vertical synchronous signal in accordance with the control signal.
A synchronous signal generation method according to a third aspect of the present invention comprises:
counting pulses of a first clock signal repeatedly in every first cycle of a supplied first horizontal synchronous signal;
counting pulses of a second clock signal in every predetermined second cycle repeatedly;
generating a second horizontal synchronous signal having the second cycle; and
controlling the second horizontal synchronous signal to synchronize with the first horizontal synchronous signal, by adjusting the second cycle in accordance with a difference between a first value obtained by counting pulses of the first clock signal and a second value obtained by counting pulses of the second clock signal.
The synchronous signal generation method may further comprise:
generating a first pulse signal having the first cycle;
generating a second pulse signal having the second cycle;
counting pulses of the first pulse signal repeatedly in every third cycle of a supplied first vertical synchronous signal;
counting pulses of the second pulse signal repeatedly in every predetermined fourth cycle;
generating a second vertical synchronous signal having the fourth cycle; and
controlling the second vertical synchronous signal to synchronize with the first vertical synchronous signal, by adjusting the fourth cycle in accordance with a difference between a third value obtained by counting pulses of the first pulse signal and a fourth value obtained by counting pulses of the second pulse signal.
The synchronous signal generation method may further comprise:
delaying the first value; and
delaying the third value.
The controlling the second horizontal synchronous signal to synchronize may comprise adjusting the second cycle in accordance with a difference between the delayed first value and the second value.
The controlling the second vertical synchronous signal to synchronize may comprise adjusting the fourth cycle in accordance with a difference between the delayed third value and the fourth value.